DocumentCode :
1195778
Title :
A New Technique for Designing High-Speed Frequency Counters
Author :
Ramachandran, Parthasarathi
Volume :
22
Issue :
3
fYear :
1973
Firstpage :
226
Lastpage :
230
Abstract :
Some basic difficulties in the implementation of high-speed frequency counters are discussed. A new method which avoids most of these difficulties is described. The method essentially consists of binary prescaling the input frequency to a value easily manageable with decade counters and subsequently multiplying the resultant count in the decade counters by the prescaling factor. A simple digit serial multiplier for this purpose is iliustrated along with the system design of a 150-MHz frequency counter. Finally, the advantages of the new approach are discussed.
Keywords :
Computer architecture; Counting circuits; Delay; Feedback; Frequency conversion; Helium; Instruments; Large scale integration; Logic; Space technology;
fLanguage :
English
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9456
Type :
jour
DOI :
10.1109/TIM.1973.4314153
Filename :
4314153
Link To Document :
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