Concurrent-error detection in high-speed carry-free dividers

Rapid advancements in technology demand innovative computation algorithms and hardware structures to achieve high performance. High-speed dividers are commonly designed using SRT division methods. Recently, a high-speed carry-free divider design using redundant binary representation has been presented. Based on the carry-free division algorithm and a more general cell-fault model instead of stuck-at fault model, the paper presents a concurrent error detection scheme using alternating input data. The key to the detection of faults is determining that at least one input combination exists for which the error does not result in alternating outputs. Results show that, with a low hardware overhead, the divider circuit is capable of detecting single/multiple transient faults in one cell during the real-time operation and enhancing its reliability significantly