DocumentCode :
1195830
Title :
Radix digit-serial pipelined divider/square-root architecture
Author :
Bashagha, A.E. ; Ibrahim, M.K.
Author_Institution :
Dept. of Electr. & Electron. Eng., Nottingham Univ., UK
Volume :
141
Issue :
6
fYear :
1994
fDate :
11/1/1994 12:00:00 AM
Firstpage :
375
Lastpage :
380
Abstract :
The paper presents a new digit-serial architecture for division and square-root which can be pipelined to the bit level to achieve high throughput. The architecture is different from the existing divider/square-root architectures in that it is based on the radix-2n algorithm. As a result, any type of adder can be used in the proposed digit-serial controlled add/subtract basic cell. The authors present two basic digit-serial controlled add/subtract cells. The first is based on the conventional carry feedback digit-serial adder. The second is based on the carry feed-forward adder, which results in the first reported digit-serial divider/square-root architecture that can be pipelined down to the bit-level. An evaluation of the proposed architecture for different values of the digit size is also presented
Keywords :
adders; digital arithmetic; adder; carry feed-forward adder; carry feedback digit-serial adder; digit-serial architecture; radix digit-serial pipelined divider/square-root architecture;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2387
Type :
jour
DOI :
10.1049/ip-cdt:19941502
Filename :
331623
Link To Document :
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