Configuration and evaluation of 2´s complement multiplication-division arrays

In the current parallel-processing devices, addition and subtraction are performed by using the 2´s complement expression. However, multiplication and division are performed by the sign-magnitude expression. The disagreement of these expressions is very inconvenient for the operations. Hence, to make them coincide with each other, we change the sign-magnitude division arrays into 2´s complement arrays, and combine division and multiplication arrays. The arrays obtained by this method are evaluated with regard to the propagation delays and required gates. In addition an extension of the arithmetic operation array is shown in the last section.