Board-level boundary scan: regaining observability with an additional IC

Author

Ballew, W. David ; Streb, Lauren M.

Author_Institution

AT&T, Oklahoma City, OK, USA

Volume

11

Issue

1

fYear

1992

fDate

1/1/1992 12:00:00 AM

Firstpage

68

Lastpage

75

Abstract

Partial implementation of boundary-scan IEEE 1149.1 at the board level has a negative effect on testability issues, economics, and total system functionality. An integrated circuit, which will allow boundary-scan architecture to interface with non-boundary-scan parts was designed to increase observability and detectability electronically. The solution offers an opportunity to fuse old and new silicon technologies into a single, hierarchical test strategy. The authors discuss the functionality, technology, and economics of a 1.25 μm CMOS application specific IC, the PROBE. The ASIC can be used to regain observability lost to higher gate-to-pin ratios and packaging density. The economic feasibility is driven by how rapidly present designs are moving forward. Successful application depends heavily on the adoption of 1149.1

Keywords

CMOS integrated circuits; application specific integrated circuits; automatic testing; economics; logic testing; observability; 1.25 micron; ASIC; CMOS; IEEE 1149.1; PROBE; application specific IC; board level; boundary-scan architecture; detectability; economic feasibility; hierarchical test strategy; integrated circuit; interface; observability; Application specific integrated circuits; CMOS integrated circuits; CMOS technology; Circuit testing; Fuses; Integrated circuit technology; Observability; Probes; Silicon; System testing;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.108619

Filename

108619