Duty-cycle controller for low-jitter frequency-doubling DLL

This article introduces a novel duty-cycle control circuit (DCC) preceding a delay-locked loop (DLL)-based clock frequency multiplier preventing the output duty-cycle over process, supply voltage and temperature (PVT) variations. However, the proposed DCC eliminates the effect of input duty-cycle variation and, hence, decreases the sensitivity to the input jitter and distortion. The circuit realisation in 0.5-μm CMOS technology shows that the duty-cycle variation at the output clock is less than 2.7%, while driving the digital section of a CODEC chip and also test pads. The analysis, confirmed by measurements, shows a stable and accurate response for the proposed clock generation unit (CGU).