Technology portable analytical model for DSM CMOS inverter delay estimation

A closed form expression to accurately estimate the delay of a CMOS deep submicron (DSM) inverter is presented. This model does not depend on extracted or fitting parameters. Instead it depends on device model parameters, and hence becomes portable across technology generations. Delay analytical model verification was performed against Spectre simulations using a BSIM3v3 model for a wide range of device sizes, capacitive loads and transition times. Model portability was tested across three DSM technologies: UMC´s 0.13 μm and TSMC´s 0.18 μm and 0.25 μm. The model exhibits high accuracy with average and maximum errors of about 2.3% and 10% compared to simulation.