Investigation of the Role of Void Formation at the Cu-to-Intermetallic Interface on Aged Drop Test Performance

Chip-scale packages (CSPs) are widely used in portable electronic products. Mechanical drop testing is a critical reliability requirement for these products. With the switch to lead-free solder, new reliability data must be generated. Most drop test reliability data reported for CSPs are for the as-built condition. However, the mechanical shock reliability over the life of the product is equally important. This paper provides a systematic study of surface finish (immersion Sn and immersion Ag) and reflow profile (cool down rate) on the drop test reliability of CSP assemblies. A limited experiment was also performed with organic solderability preservative (OSP)-coated boards. The Sn finish provides an initial Cu-Sn intermetallic layer, while the Ag finish and OSP coating allows the formation of the initial Cu-Sn intermetallic during the reflow cycle. Drop test results for assemblies as-built and as a function of aging at 125 degC are correlated with cross-sectional analysis of the solder joints. The mean number of drops to failure decreases by approximately 80% with aging at 125 degC through 480 h. Voids develop at the Cu-Sn intermetallic-to-Cu interface during high-temperature aging, but the crack path is through the intermetallic layer and does not propagate from void-to-void. Thus, it can be concluded that the voids do not contribute to the decrease in drop test survivability observed in this study