• DocumentCode
    1198974
  • Title

    Programmable DSP architectures. II

  • Author

    Lee, Edward A.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • Volume
    6
  • Issue
    1
  • fYear
    1989
  • Firstpage
    4
  • Lastpage
    14
  • Abstract
    For pt.I see ibid., vol.5, no.4, p.4-19, Oct. 1988. Three distinct techniques are used for dealing with pipelining, namely, interlocking, time-stationary coding, and data-stationary coding, are examined. These techniques are studied in light of the performance benefit and the impact on the user. Representative DSPs from AT&T, Motorola, and Texas Instruments are used to illustrate the ideas and compare different solutions to the same problems. Trends are discussed, and some predictions for the future are made.<>
  • Keywords
    computer architecture; digital signal processing chips; encoding; pipeline processing; AT&T; Motorola; Texas Instruments; data-stationary coding; interlocking; pipelining; programmable DSP architecture; time-stationary coding; Arithmetic; Bandwidth; Decoding; Digital signal processing; Digital signal processors; Instruments; Manufacturing; Pipeline processing; Programming profession; Timing;
  • fLanguage
    English
  • Journal_Title
    ASSP Magazine, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7467
  • Type

    jour

  • DOI
    10.1109/53.16934
  • Filename
    16934
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1198974