Mixed body bias techniques with fixed Vt and Ids generation circuits

There remains a need to improve sub-1-V CMOS VLSIs with respect to variation in transistor behavior. In this paper, to minimize variation in delay and the noise margin of the circuits in processors, we propose several mixed body bias techniques using body bias generation circuits. In these circuits, either the saturation region of the current between source and drain (I_ds) or the threshold voltage (V_t) of PMOS/NMOS is permanently fixed, regardless of temperature range or variation in process. A test chip that featured these body bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well structure. The mixed body bias techniques which keep the I_ds of the MOS in the decoder and I/O circuits of a register file fixed and maintain the V_t of the MOS in both the memory cell and domino circuits of the register file fixed resulted in positive temperature dependence of delay from -40 °C to 125 °C, 85% reduction of the delay variation compared with normal body bias (NBB) at V_DD = 0.8 V. In addition, the results using these techniques show a 100-mV improvement in lower operating voltage compared with NBB at -40 °C on a 4-kb SRAM.