• DocumentCode
    1199441
  • Title

    Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry

  • Author

    Acharyya, Amit ; Maharatna, Koushik ; Al-Hashimi, Bashir M. ; Gunn, Steve R.

  • Author_Institution
    Sch. of Electron. & Comput. Sci., Univ. of Southampton, Southampton
  • Volume
    56
  • Issue
    4
  • fYear
    2009
  • fDate
    4/1/2009 12:00:00 AM
  • Firstpage
    285
  • Lastpage
    289
  • Abstract
    In this brief, we show that by exploiting the inherent symmetry of the discrete wavelet transform (DWT) algorithm and consequently storing only the nonrepetitive combinations of filter coefficients, the size of required memory can be significantly reduced. Subsequently, a memory-efficient architecture for DWT/inverse DWT is proposed. It occupies 6.5-mm2 silicon area and consumes 46.8-muW power at 1 MHz for 1.2 V using 0.13-mum standard cell technology.
  • Keywords
    VLSI; discrete wavelet transforms; distributed algorithms; low-power electronics; discrete wavelet transform; distributed arithmetic; exploiting data symmetry; filter coefficients; memory reduction methodology; multiplierless implementation; Distributed arithmetic (DA); low-power architecture; multiplierless implementation; very large scale integration; wavelet;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2009.2015386
  • Filename
    4803792
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1199441