Fast Modulo 2^{n} - (2^{n - 2} + 1) Addition: A New Class of Adder for RNS

Author

Patel, R.A. ; Benaissa, M. ; Boussakta, S.

Author_Institution

Dept. of Electron. & Electr. Eng., Univ. of Sheffield

Volume

56

Issue

4

fYear

2007

fDate

4/1/2007 12:00:00 AM

Firstpage

572

Lastpage

576

Abstract

Efficient modular adder architectures are invaluable to the design of residue number system (RNS)-based digital systems. For example, they are used to perform residue encoding and decoding, modular multiplication, and scaling. This work is a first in the literature on modulo 2ⁿ-(2^n-2+1) addition. The algebraic properties of such moduli are exploited in the derivation of the proposed fast adder architecture. Actual VLSI implementations using 130 mm CMOS technology show that our adder significantly outperforms the most competitive generic modular adder design over the entirety of the power-delay-area space

Keywords

VLSI; adders; carry logic; residue number systems; CMOS technology; VLSI implementation; computer arithmetic; digital system; modular adder architecture; modular multiplication; power-delay-area space; residue decoding; residue encoding; residue number system; Adders; Arithmetic; CMOS technology; Decoding; Digital signal processing; Digital systems; Dynamic range; Space technology; Table lookup; Very large scale integration; Computer arithmetic; VLSI.; modular adder; parallel-prefix adder; residue number system;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.2007.1001

Filename

4118680