Title :
A 0.18-/spl mu/m 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)
Author :
Woo Yeong Cho ; Beak-Hyung Cho ; Byung-Gil Choi ; Hyung-Rok Oh ; Sangbeom Kang ; Ki-Sung Kim ; Kyung-Hee Kim ; Du-Eung Kim ; Choong-Keun Kwak ; Hyun-Geun Byun ; Youngnam Hwang ; Ahn, S. ; Gwan-Hyeob Koh ; Gitae Jeong ; Hongsik Jeong ; Kinam Kim
Author_Institution :
Memory Div., Samsung Electron. Co. Ltd., Gyeonggi-Do, South Korea
Abstract :
A nonvolatile 64-Mb 1T1R phase-transition random access memory (PRAM) has been developed by fully integrating chalcogenied storage material (GST: Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18-/spl mu/m CMOS technology. To optimize SET/RESET distribution, 512-kb sub-array core architecture was proposed, featuring meshed ground line and separated SET/RESET control schemes. Random read access time, random SET and RESET write access times were measured to be 60 ns, 120 ns, and 50 ns, respectively, at 3.0-V supply voltage with 30/spl deg/ C.
Keywords :
CMOS memory circuits; chalcogenide glasses; germanium compounds; random-access storage; 0.18 micron; 120 ns; 3.0 V; 30 C; 50 ns; 60 ns; 64 Mbits; Ge/sub 2/Sb/sub 2/Te/sub 5/; SET/RESET distribution; meshed ground line; nonvolatile phase-transition random access memory; phase change; sub-array core architecture; CMOS technology; Crystallization; Flash memory; Heating; Material storage; Nonvolatile memory; Phase change random access memory; Random access memory; Tellurium; Temperature; Phase change; RESET; SET; phase-transition random access memory (PRAM);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.837974
