Estimating Error Rate in Defective Logic Using Signature Analysis

As feature size approaches molecular dimensions and the number of devices per chip reaches astronomical values, VLSI manufacturing yield significantly decreases. This motivates interests in new computing models. One such model is called error tolerance. Classically, during the postmanufacturing test process, chips are classified as being bad (defective) or good. The main premise in error-tolerant computing is that some bad chips that fail classical go/no-go tests and do indeed occasionally produce erroneous results actually provide acceptable performance in some applications. Thus, new test techniques are needed to classify bad chips according to categories based upon their degree, of acceptability with respect to predetermined applications. One classification criterion is error rate. In this paper, we first describe a simple test structure that is a minor extension to current scan-test and built-in self-test structures and that can be used to estimate the error rate of a circuit. We then address three theoretical issues. First, we develop an elegant mathematical model that describes the key parameters associated with this test process and incorporates bounds on the error in estimating error rate and the level of confidence in this estimate. Next, we present an efficient testing procedure for estimating the error rate of a circuit under test. Finally, we address the problem of assigning bad chips to bins based on their error rate. We show that this can be done in an efficient, hence cost-effective, way and discuss the quality of our results in terms of such concepts as increase effective yield, yield loss, and test escape