Optimal cell generation for dual independent layout styles

Many optimization algorithms have been proposed for layout styles which are dual dependent: that is, the optimization for the layout of the n-transistor network of a CMOS complex gate is dependent on, the p-transistor network and vice versa. A two-stage linear-time optimization algorithm for dual independent layout styles is presented. The first stage is based on a tree representation of the complex gate. This tree representation allows complete flexibility in transistor order and takes complete advantage of the concept of delayed binding. The optimization goal is identical to the Euler pathed optimization algorithms metal-metal matrix (M³) layout style, and examples of generated layouts are shown. Starting from a switching expression, the proposed algorithm always produces an optimal solution in terms of the number of diffusion breaks, which includes an optimal transistor representation for the switching expression (first stage), and an optimal gate sequence to traverse this transistor circuit (second stage)