• DocumentCode
    1200156
  • Title

    Benefits of a SoC-specific test methodology

  • Author

    Quasem, Md Saffat ; Jiang, Zhigang ; Gupta, Sandeep K.

  • Volume
    20
  • Issue
    3
  • fYear
    2003
  • Firstpage
    68
  • Lastpage
    77
  • Abstract
    The tradeoff between IP protection and SoC-level test optimization has been an issue for some time. The more IP providers protect their IP, the less flexibility system developers have to control test costs and fault coverage. In this paper, a new approach dynamically extracts IP-related test information or optimizing SoC testing without jeopardizing IP protection.
  • Keywords
    electronic engineering computing; integrated circuit testing; system-on-chip; IP protection; SoC-level test optimization; SoC-specific test methodology; fault coverage; Circuit faults; Circuit testing; Control systems; Design for testability; Information analysis; Logic testing; Optimization methods; Pattern analysis; Protection; System testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2003.1198688
  • Filename
    1198688
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1200156