Abstract :
As semiconductor technology has matured, the advent of LSI chips such as microprocessors with substantially increased device functionality and complexity has created unparalleled challenges to test philosophy. Most traditional screening techniques become inadequate in defining the worst cases of test patterns and test sequences out of an enormous number of sequential-combinational candidates and in tracking reliability data following the various stages of product life to provide corrective action. A computerized automatic-optimization strategy is conceived using a systematic approach based on statistical, cumulative and time dependent processes. It integrates device characterization, on-line screening, product and subsequent reliability monitoring via distributed data base management in a closed-loop self-corrective manner. Preliminary evaluation of the intelligent test pattern/sequence generation has been conducted for on-line device screening; the conceived algorithms detects 99 percent of the total defects and consumes only 10 percent test-time of the conventional approach, a significant savings in cost, labor, and equipment expenditure requirement. This test strategy shows the approach to combat ever increasing device complexity while still providing a substantially improved performance-to-cost ratio.
