Title :
Automatic extraction of circuit models from layout artwork for a BiCMOS technology
Author :
Hook, Terence B.
Author_Institution :
IBM, Essex Junction, VT, USA
fDate :
6/1/1992 12:00:00 AM
Abstract :
An approach to modeling BiCMOS circuitry in which a simulation card desk is produced directly from the circuit layout artwork is described. The cards contain sufficient information about the device dimensions and net interconnections to form a complete circuit model. The approach allows extensive integration of the devices into an optimal layout and includes the interaction of a PFET and an NPN built in the same well. The active device menu includes NFETs, PFETs, NPNs, and resistors. Parasitic capacitances associated with the source and drain diffusions are calculated and a resistor mesh in the subcollector is created. The individual steps leading to the formation of the circuit model are described, and examples of bipolars and BiCMOS circuits are shown
Keywords :
BIMOS integrated circuits; circuit layout CAD; semiconductor device models; BiCMOS technology; active device menu; circuit models; device dimensions; layout artwork; net interconnections; parasitic capacitances; resistor mesh; simulation card desk; subcollector; BiCMOS integrated circuits; CMOS technology; Circuit simulation; Data mining; Flexible printed circuits; Integrated circuit interconnections; Resistors; Semiconductor device modeling; Shape; Wiring;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
