DocumentCode
1201158
Title
Count-based BIST compaction schemes and aliasing probability computation
Author
Ivanov, André ; Zorian, Yervant
Author_Institution
Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
Volume
11
Issue
6
fYear
1992
fDate
6/1/1992 12:00:00 AM
Firstpage
768
Lastpage
777
Abstract
The authors present a unified probabilistic model of count-based compaction that relates the probability of occurrence of the counted events to a circuit´s fault detection probabilities. This model allows an identical treatment of all the different count-based techniques proposed to date, e.g. ones, transitions, edges, and spectral coefficients, by essentially reducing all techniques to simple ones-counting. From a Markov model of ones-counting, the authors derive asymptotic aliasing probabilities, and for finite test sequence lengths they developed a computation technique for determining the aliasing associated with the specifically mentioned schemes, as well as more general count-based compaction techniques, under various error models
Keywords
Markov processes; built-in self test; probability; BIST compaction schemes; Markov model; aliasing probability computation; count-based compaction; error models; fault detection probabilities; finite test sequence lengths; unified probabilistic model; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Computer errors; Electrical fault detection; Integrated circuit testing; Performance analysis; Polynomials;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.137522
Filename
137522
Link To Document