Title :
Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks
Author :
Bryan, Michael J. ; Devadas, Srinivas ; Keutze, Kurt
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
fDate :
6/1/1992 12:00:00 AM
Abstract :
The authors address the problem of synthesizing circuits that are highly testable for transistor stuck-open fault testability in arbitrary, multilevel networks. They consider single stuck-open faults that are detectable using two-pattern tests, under a robust fault model wherein hazards, races, or glitches cannot invalidate a test. Using these results the authors show that algebraic factorization, including the constrained use of the complement, can be used to synthesize fully-stuck-open-fault testable multilevel networks. They provide a comprehensive set of practical results
Keywords :
hazards and race conditions; logic design; logic testing; many-valued logics; algebraic factorization; hazard-free test; multilevel networks; robust fault model; stuck-open-fault testability; two-pattern tests; Circuit faults; Circuit synthesis; Circuit testing; Hazards; Logic testing; Network synthesis; Robustness; Sufficient conditions; Terminology; Timing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
