False coupling exploration in timing analysis

As integrated circuit technology continues to scale into the nanometer regime, the effect of crosstalk on circuit timing becomes significant. Static timing analysis shows that crosstalk routinely adds 10% to 20% delay to the critical path of a design. However, many aggressor/victim switching combinations are infeasible due to inherent circuit operating constraints, thereby contributing to the mismatch between timing analysis and actual silicon performance. This paper proposes a novel timing analysis technique where circuit functionality, delay, and crosstalk are simultaneously considered using time-sliced Boolean logic. The worst case timing on the critical path end point is calculated to be the minimum and maximum time slices where the timed Boolean logic on its coupled fanin cone is satisfiable. Up to 1-ns reduction in timing pessimism on 0.13-μm industrial designs was observed. Furthermore, results on special circuit topologies such as data busses with coupled interleaved inverters match well with results from exhaustive Spice simulation sweeps with up to 50% reduction in timing pessimism over timing analysis that does not consider false coupling.