Statistical Analysis of Transistor-Resistor Logic Networks

This paper describes a general approach to statistical investigation of properties of complex transistor switching networks. In particular, we are concerned with TRL circuits which use resistive coupling between grounded emitter stages to perform the logical NOR function. An important consideration in the design of TRL systems is the delay in propagating signals through various levels of these circuits. A mathematical model of the delay has been constructed which is a complicated function of circuit variables as well as of the intrinsic parameters of the transistors involved. A computer program was written to simulate the model on an IBM 709. By using measured statistical data of transistor parameters and randomly sampled circuit variables as input, a Monte Carlo analysis of the distribution of propagation delay is carried out.