Digital Frequency Multiplier for Spectrum Measurement of Periodic Signals

Frequency multipliers find applications in the Fourier and Walsh spectrum measurements of periodic signals. Earlier digital frequency multipliers use two counters: 1) An upcounter which is partitioned into a fractional counter of kbits in cascade with an integral counter. This determines the period of the input signal by the number of clock pulses that are accumulated in a period of the signal. 2) A downcounter which is next fed from the same clock, and which is periodically preset to the contents of the integral counter whenever the downcounter reaches zero. In this process an error is introduced in the output frequency because the fractional counter contents are ignored in the frequency multiplication phase. To minimize this error, a high clock frequency is required so that the fractional count is small compared with the integral count. The maximum output pulse frequency is limited by the speed of the counters used. A new method is described which also uses the contents of the fractional counter. The clock frequency is reduced substantially and the maximum output pulse frequency is limited by the settling time of a D/A converter: If the settling time is 200 ns, the maximum output frequency is ten times that of earlier methods.