DocumentCode
1202504
Title
Secondary radix recodings for higher radix multipliers
Author
Seidel, Peter-Michael ; McFearin, Lee D. ; Matula, David W.
Author_Institution
Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
Volume
54
Issue
2
fYear
2005
Firstpage
111
Lastpage
123
Abstract
For progressively higher radices, the reduction in partial products obtained by the well-known modified Booth multiplier recoding is offset by the need to precompute a rapidly increasing store of odd multiples of the multiplicand as inputs to each partial product generator (PPG). We propose secondary radix multiplier recoding schemes reducing the number of odd multiples required in the store for very high radix recodings (e.g., radix 2r for 5 ≤ r ≤ 16). The proposed recoding schemes allow reduction of the number of partial products in the implementation by factors between and beyond the reduction factors of 2, 3, and 4 that can be achieved by traditional Booth recodings to radices 4, 8, and 16, respectively. We develop the theory of these recodings and provide methodology for secondary radix selection. Finally, we summarize latency and cost evaluations of selected implementations indicating potential cost and performance/cost advantages for practical operand sizes.
Keywords
adders; digital arithmetic; multiplying circuits; Booth multiplier recoding; binary multiplication; high radix recodings; mixed radix representation; partial product generator; partial product reduction; secondary radix multiplier recoding scheme; Clocks; Costs; Delay; Frequency; Hardware; Microprocessors; Pipelines; Process design;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/TC.2005.32
Filename
1377150
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