A physical and circuit level approach for modeling turn-off characteristics of GTOs

In this paper, we present physical and circuit models, which are related via their parameters, to characterize the gated turn-off characteristics of thyristors. The physical model provides physical insight to the mechanism of turn-off in single islands, and investigates analytically, the dependence of storage time on external variables (anode and gate currents) and physical device parameters and dimensions. Such a characterization is useful since the current crowding effect (that limits current controllability in a multi-emitter structure) depends on the turn-off behavior of the unit cells. The circuit level approach provides a model which can be incorporated into CAD programs (such as SPICE) that can be used by application engineers to design a variety of power electronic circuits such as static VAr compensators (SVCs), The parameters of the circuit model are based on the physical model parameters and thus reflect the physical device properties and dimensions