A 2.4 GHz CMOS sub-sampling mixer with integrated filtering

Author

Pekau, Holly ; Haslett, James W.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Calgary, Alta., Canada

Volume

40

Issue

11

fYear

2005

Firstpage

2159

Lastpage

2166

Abstract

A sub-sampling mixer that incorporates sampling switches and hold capacitors into the parallel resonant LC load of an LNA is proposed. The noise figure of the proposed sub-sampling mixer is lower than that of a standard sampling circuit because the proposed mixer has narrow-band gain and input noise filtering properties. A novel level-shifting clock buffer with fast rise and fall times to drive the mixer sampling switches is presented. The mixer was fabricated in a 0.18 μm CMOS process and measured results are presented for an RF input frequency of 2.42 GHz and a sampling frequency of 100 MHz. With a measured noise figure of 21.8 dB, the proposed circuit shows improved performance compared to other published sub-sampling mixers.

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; UHF mixers; integrated circuit design; integrated circuit noise; sample and hold circuits; 0.18 micron; 100 MHz; 2.42 GHz; 21.8 dB; CMOS analog integrated circuits; CMOS sub-sampling mixer; LC filters; bandpass sampling; communication circuits; integrated circuit noise; integrated filtering; level-shifting clock buffer; low noise amplifier; mixer sampling switches; noise aliasing; parallel resonant LC load; standard sampling circuit; track-and-hold circuits; Capacitors; Circuits; Clocks; Filtering; Frequency; Narrowband; Noise figure; Resonance; Sampling methods; Switches; Bandpass sampling; CMOS analog integrated circuits; LC filters; communication circuits; integrated circuit noise; noise aliasing; sub-sampling mixers; track-and-hold circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.857364

Filename

1522555