Title :
A monotonic digitally controlled delay element
Author :
Maymandi-Nejad, Mohammad ; Sachdev, Manoj
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Ont., Canada
Abstract :
A monotonic digitally controlled delay element (DCDE) is implemented in the 0.18 μm CMOS technology. In this paper, the design procedure of the new architecture and measurement results are reported. The delay of the DCDE changes monotonically with respect to the digital input vector. The monotonicity is one of the important features of this new architecture. Due to its monotonic behavior, the design of the DCDE is rather straightforward. The DCDE can be analyzed by a simple set of empirical equations with reasonable accuracy and can be made more tolerant to process, temperature, and supply voltage variations. The implemented delay element provides a delay resolution of as low as 2 ps and consumes 170 μW to 340 μW static power depending on the digital input vector.
Keywords :
CMOS digital integrated circuits; delay lock loops; integrated circuit design; low-power electronics; 0.18 micron; 170 to 340 muW; CMOS integrated circuits; DCDE design; delay circuits; delay-locked loops; digital input vector; monotonic digitally controlled delay element; monotonicity; programmable delay; static power; CMOS technology; Circuit testing; Delay; Digital control; Equations; Inverters; MOSFETs; Switches; Very large scale integration; Voltage control; CMOS integrated circuits; delay circuits; delay-locked loops; programmable delay; test;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2005.857370
