A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning

Author

Iida, Masahisa ; Kuroda, Naoki ; Otsuka, Hidefumi ; Hirose, Masanobu ; Yamasaki, Yuji ; Ohta, Kiyoto ; Shimakawa, Kazuhiko ; Nakabayashi, Takashi ; Yamauchi, Hiroyuki ; Sano, Tomohiko ; Gyohten, Takayuki ; Maruta, Masanao ; Yamazaki, Akira ; Morishita, Fu

Author_Institution

Corp. Syst. LSI Dev. Div., Syst. LSI Technol. Dev. Center, Kyoto, Japan

Volume

40

Issue

11

fYear

2005

Firstpage

2296

Lastpage

2304

Abstract

A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to save the data retention power down to 60 μW are achieved.

Keywords

CMOS logic circuits; DRAM chips; embedded systems; low-power electronics; 16 Mbyte; 322 MHz; 90 nm; CMOS logic; embedded DRAM; logic compatibility; low noise core architecture; sensing accuracy; tuning scheme; twisted bit-line; CMOS process; Capacitance; Costs; Delay; Large scale integration; Logic; Noise generators; Noise level; Random access memory; Semiconductor device noise; DRAM; logic compatibility; low power; noise cancel; tuning; twisted bit-line;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2005.857358

Filename

1522569