Title :
Prescaler using complementary clocking dynamic flip-flop
Author :
Han, Seon-Ho ; Youn, Yong-Sik ; Kim, Cheon-Soo ; Yu, Hyun-Ku ; Park, Mun-Yang
Author_Institution :
Electron. & Telecommun. Res. Inst., Taejeon, South Korea
fDate :
5/1/2003 12:00:00 AM
Abstract :
A prescaler using complementary clocking dynamic flip-flops (CCD-FF) is presented and implemented in a synthesiser using 0.18 μm CMOS technology. The maximum operating frequency of the proposed CCD-FF is up to about 10 GHz and the prescaler using this flip-flop operates up to 5.1 GHz. The proposed CCD-FF has not only a high operating frequency but also low power consumption since it is based on the scheme of the conventional true single phase clocking (TSPC) flip-flop with no static DC current. The RMS current consumption of designed 16/17 dual-modulus prescaler is only 1.39 mA at 4 GHz.
Keywords :
CMOS logic circuits; flip-flops; low-power electronics; prescalers; sequential circuits; 0.18 micron; 1.39 mA; 10 GHz; 4 GHz; 5.1 GHz; CMOS; RMS current consumption; complementary clocking dynamic flip-flop; operating frequency; power consumption; prescaler; true single phase clocking;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20030478
