Abstract :
A novel multilevel metallization scheme has been developed that uses tungsten for the primary level of interconnection. Grooves that are 1-μm wide and 2.0-μm deep, corresponding to a level of line conductor interconnection, are pattern-etched into a planar layer of oxide dielectric. They are filled by isotropically depositing a blanket layer of pure tungsten using low-pressure chemical vapor deposition (CVD), followed by etch-back of the tungsten to produce a filled-interconnection-groove (FIG) conductor structure. Fabricated FIG conductors display an average sheet resistivity of 48 mΩ/square, comparable to conventional aluminum conductors. In addition, FIG metallization provides excellent planarity and greatly improved electromigration strength, and it facilitates the use of stacked vias
Keywords :
VLSI; chemical vapour deposition; integrated circuit technology; metallisation; tungsten; 1 micron; 2 micron; CVD; FIG; FIG conductors; FIG metallization; W metallisation; electromigration strength; etch-back; filled interconnect groove metallization; low-pressure chemical vapor deposition; multilevel metallization scheme; planar layer of oxide dielectric; planarity; sheet resistivity; use of stacked vias; Aluminum; Chemical vapor deposition; Conductivity; Conductors; Dielectrics; Displays; Electromigration; Etching; Metallization; Tungsten;
