Efficient montgomery multiplier for pairing and elliptic curve based cryptography

In this paper, we propose an efficient 256×256 bit modular multiplier based on Montgomery reduction algorithm. The 256 × 256 bit modular multiplier is required in elliptic curve and pairing based cryptographic protocols to achieve 128 bit security level. The in-built features of modern FPGA are efficiently utilized. Two time consuming components (1) 512-bit addition (2) 256 × 256 bit multiplier are efficiently optimized. The 512-bit addition is optimized using 64-bit carry chains while the 64 × 64 bit multiplier soft cores provided by Xilinx FPGAs are utilized to design the 256 × 256 bit multiplier. Subsequently, both the adder and multiplier are used to design 256-bit modular multiplier using Montgomery reduction algorithm. The design is synthesized using Xilinx ISE 14.1 design suite targeting virtex 6 FPGA devices. The proposed design runs at 188 MHz and can be used to construct elliptic curve and pairing based cryptographic processors.