A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS

Author

Van De Vel, Hans ; Buter, Berry A J ; Van der Ploeg, Hendrik ; Vertregt, Maarten ; Geelen, Govert J G M ; Paulus, Edward J F

Author_Institution

NXP Semicond., Eindhoven

Volume

44

Issue

4

fYear

2009

fDate

4/1/2009 12:00:00 AM

Firstpage

1047

Lastpage

1056

Abstract

This paper describes a digitally calibrated pipeline analog-to-digital converter (ADC) implemented in 90 nm CMOS technology with a 1.2 V supply voltage. A digital background calibration algorithm reduces the linearity requirements in the first stage of the pipeline chain. Range scaling in the first pipeline stage enables a maximal 1.6 V_pp input signal swing, and a charge-reset switch eliminates ISI-induced distortion. The 14b ADC achieves 73 dB SNR and 90 dB SFDR at 100 MS/s sampling rate and 250 mW power consumption. The 73 dB SNDR performance is maintained within 3 dB up to a Nyquist input frequency and the FOM is 0.68 pJ per conversion-step.

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; power consumption; 90-nm CMOS technology; digital background calibration algorithm; digitally calibrated pipeline ADC; digitally calibrated pipeline analog-to-digital converter; power consumption; voltage 1.2 V; Analog-digital conversion; CMOS technology; Calibration; Distortion; Energy consumption; Linearity; Pipelines; Sampling methods; Switches; Voltage; ADC; CMOS analog integrated circuits; analog-to-digital conversion; calibration; charge reset; low power; low voltage; pipeline; range scaling;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2009.2014702

Filename

4804968