Title :
A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS
Author :
Iwata, Kenichi ; Mochizuki, Seiji ; Kimura, Motoki ; Shibayama, Tetsuya ; Izuhara, Fumitaka ; Ueda, Hiroshi ; Hosogi, Koji ; Nakata, Hiroaki ; Ehama, Masakazu ; Kengaku, Toru ; Nakazawa, Takuichiro ; Watanabe, Hiromi
Author_Institution :
Renesas Technol. Corp., Tokyo
fDate :
4/1/2009 12:00:00 AM
Abstract :
A video-size-scalable H.264 high-profile codec including 19 application-specific CPUs for extensibility to multiple standards has been fabricated in 65 nm CMOS. With two parallel pipelines for macroblock processing, the codec consumed 256 mW in real-time encoding of 40 Mbp full-HDs (1080p30) video at an operating frequency of 162 MHz.
Keywords :
CMOS integrated circuits; video codecs; dual-macroblock pipeline architecture; frequency 162 MHz; macroblock processing; video-size-scalable H.264 high-profile codec; Circuits; Code standards; Energy consumption; Frequency; High definition video; Image coding; Pipelines; Streaming media; Video codecs; Video coding; H.264; full HD; low power consumption; mobile applications; multiple video standard; video codec;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2014025
