Two-dimensional numerical analysis of the floating region in SOI MOSFETs

Results of simulating SOI/MOSFET (silicon-on-insulator/metal-oxide-semiconductor field-effect-transistor) devices using the full two-dimensional numerical solution of the classical semiconductor equations are presented. Particular attention has been paid to the role of the floating region, and it is demonstrated that removal of this phenomenon is important for the improvement of the performance of SOI/MOSFET devices. Several methods, such as applying a back gate bias or using thinner (100-nm) films, are investigated as a means of controlling this undesirable feature. It is shown that the use of thin films has major advantages. It is concluded from a study of the effect of lifetime on device performance that improved film quality can have an adverse effect on the I_d-V_d characteristics, giving an enhanced kink and earlier breakdown on 0.3-μm silicon films