Design and performance analysis of a nanoscaled inverter based on wrap-aroundgate nanowire MOSFETs

Author

Seyedi, Alireza ; Pavel, A.A. ; Sharma, Arvind Kumar ; Islam, Naz E.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Southern California, Los Angeles, CA

Volume

4

Issue

1

fYear

2009

fDate

3/1/2009 12:00:00 AM

Firstpage

16

Lastpage

21

Abstract

The design and analysis of a silicon nanowire inverter with a wrap-around-gate nMOS is presented and its performance is compared with that of a conventional inverter. The analysis shows that the nano-channel structure design can improve carrier mobility by suppressing the transverse component of the electric field. This results in an enhancement in the current drive of the nMOS, and contributes to lowering power consumption and the switching delay. Simulated power consumption and rise time of the proposed design was found to be about 20 muW and 0.5 ns, respectively, compared with 2.5 mW and 1.5 ns achievable with conventional planar MOSFETs. Investigation of the gate length shows that a nMOS with shorter gates have an improved switching response compared with long channel devices.

Keywords

MOSFET; carrier mobility; invertors; low-power electronics; nanoelectronics; nanowires; semiconductor device models; silicon; Si; carrier mobility; electric field transverse component; nMOS current drive; nMOS gate length; nanochannel structure design; nanoscaled inverter performance analysis; power 20 muW; silicon nanowire inverter design; simulated power consumption; switching delay; time 0.5 ns; wrap-around-gate nMOS; wrap-around-gate nanowire MOSFET;

fLanguage

English

Journal_Title

Micro & Nano Letters, IET

Publisher

iet

ISSN

1750-0443

Type

jour

DOI

10.1049/mnl:20080046

Filename

4805244