A low power DLL based clock multiplier for multistandard wireless smart grid communication

This paper presents a low power clock multiplier circuit to be used in multistandard transceivers. The circuit is based on a delay locked loop (DLL) and can be used to multiply the input clock reference by 2, 3, 4 5 or 6. The offered clock multiplier circuit is targetted for multistandard System-on-Chip´s to be used in smart grid communication. For an input clock reference of 32 MHz, the clock multiplier achieves an output phase noise of -144 dBC/√Hz at 100 KHz offset while consuming 500 μA from a 1.2 V supply. The achieved performance results are given after post layout simulations by using UMC 130nm CMOS technology.