Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial-Response Channels

Low-complexity bit-by-bit detection techniques for 1-D partial-response channels are presented. First, a full-rate detection technique is presented which operates at 3.3 Gb/s consuming 40 mA from a 1.8-V supply with a sensitivity of 40-mV differential. The speed of the full-rate architecture is limited by the settling time of a latch circuit which has to be less than 1 UI. To eliminate this limitation, a novel demuxing technique is introduced. Using the proposed technique, a second architecture achieves 5 Gb/s data rate with the same sensitivity and consuming 62 mA (including output buffer) from 1.8-V supply. Both half-rate and full-rate architectures are also studied in 90-nm CMOS targeting chip-to-chip applications. The implemented full-rate architecture operates at 10 Gb/s consuming 32 mW, whereas the simulated half-rate architecture consumes 50 mW and operates at 16.67 Gb/s.