Title :
Plasma Doping of InGaAs at Elevated Substrate Temperature for Reduced Sheet Resistance and Defect Formation
Author :
Kong, Eugene Y.-J ; Subramanian, Sivaraman ; D´Costa, Vijay Richard ; Lye-Hing Chua ; Wei Zou ; Chan, Chi Hou ; Henry, Todd ; Yee-Chia Yeo
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore
Abstract :
Plasma doping (PLAD), a high-throughput ion implantation technique capable of achieving ultrashallow junctions and conformal doping of 3-D structures such as fin field-effect transistors, is investigated as an alternative to conventional beam-line ion implantation for InGaAs at advanced technology nodes. The PLAD at an elevated substrate temperature (ET-PLAD) is studied and reported for InGaAs for the first time. The ET-PLAD can give lower sheet resistance than room-temperature PLAD due to enhanced dopant incorporation. More crucially, an ET can help to prevent amorphization. After dopant activation anneal, residual corner defects are observed in small fins that are amorphized during plasma ion implantation, whereas fins that remain crystalline during plasma ion implantation are free of corner defects.
Keywords :
III-V semiconductors; MOSFET; doping; gallium arsenide; indium compounds; ion implantation; 3-D structures; InGaAs; amorphization; beam-line ion implantation; conformal doping; defect formation; dopant activation anneal; elevated substrate temperature; fin field-effect transistors; ion implantation technique; plasma doping; plasma ion implantation; residual corner defects; sheet resistance; temperature 293 K to 298 K; Doping; Implants; Indium gallium arsenide; Ion implantation; Plasmas; Silicon; Substrates; III–V; III-V; InGaAs; plasma doping (PLAD); substrate temperature;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2014.2341619