An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique

Author

Lin, Jerry ; Haroun, Baher

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

Volume

37

Issue

12

fYear

2002

fDate

12/1/2002 12:00:00 AM

Firstpage

1610

Lastpage

1617

Abstract

For high-data-rate wireless communication, low-voltage baseband converters integrated with DSP in deep submicrometer processes are area- and power-efficient. Through careful architecture selections and circuit techniques, this paper demonstrates a low-voltage (0.8 V), low-power (480 μW), 6-b/22-MHz flash-interpolation ADC which occupies 0.3 mm² and achieves 33 dB SNDR and 47 dB SFDR. The power efficiency of this converter is 0.6 pJ/conv-step which compares favorably with all published results. We also introduce a nonlinear double interpolation technique that enables the use of a 0.13-μm standard digital CMOS process without special resistors.

Keywords

CMOS integrated circuits; VLSI; analogue-digital conversion; interpolation; low-power electronics; 0.13 micron; 0.8 V; 22 MHz; 480 muW; 6 bit; DSP; SFDR; SNDR; architecture selections; circuit techniques; deep submicrometer processes; digital CMOS process; flash-interpolation ADC; low-voltage baseband converters; nonlinear double interpolation technique; power efficiency; Baseband; CMOS process; Circuits; Costs; Digital signal processing; Digital signal processing chips; High power amplifiers; Interpolation; Noise generators; Radio frequency;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2002.804333

Filename

1088087