Title :
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies
Author :
Chen, Yiran ; Li, Hai ; Roy, Kaushik ; Koh, Cheng-Kok
Author_Institution :
Seagate Technol., Bloomington, MN, USA
Abstract :
To minimize the leakage power dissipation of present-day on-chip Decaps, we propose a gated decoupling capacitor (GDecap) technique that deactivates a Decap when it is not needed. The application of the proposed GDecap technique on an eight-way clock-gated clustered pipeline showed that on average, 41.7% Decap leakage power was reduced, with negligible (~ 0.037%) worst-case performance degradation, at the 70-nm technology node. GDecap design incurred an area overhead of around 5.36% when compared with a conventional Decap design.
Keywords :
VLSI; capacitors; clocks; low-power electronics; scaling circuits; VLSI; eight-way clock-gated clustered pipeline; gate leakage control; gated decoupling capacitor technique; leakage power dissipation minimization; low-power design; on-chip Decap design; power supply network; size 70 nm; Capacitance; VLSI; low-power design;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2008.2007843
