Title :
A quadruple well, quadruple polysilicon BiCMOS process for fast 16 Mb SRAM´s
Author :
Hayden, James D. ; Taft, Robert C. ; Kenkare, P. ; Mazure, C. ; Gunderson, C. ; Nguyen, B.Y. ; Woo, M. ; Lage, C. ; Roman, Bernard J. ; Radhakrishna, S. ; Subrahmanyan, R. ; Sitaram, A.R. ; Pelley, P. ; Lin, J.-H. ; Kemp, Kevin ; Kirsch, H.
Author_Institution :
Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA
fDate :
12/1/1994 12:00:00 AM
Abstract :
An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM´s. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm2 with conventional I-line lithography and 7.32 μm2 with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance
Keywords :
BiCMOS memory circuits; SRAM chips; integrated circuit technology; isolation technology; photolithography; 0.8 to 1.0 micron; 16 Mbit; I-line lithography; MOSFET transistors; PELOX isolation; SRAMs; active pitch; aggressively scaled parasitics; cell area; deep UV lithography; double polysilicon bipolar transistor; quadruple polysilicon BiCMOS process; quadruple well process; self-aligned contacts; split word-line bitcell architecture; thin-film polysilicon transistor; BiCMOS integrated circuits; Bipolar transistors; Implants; Isolation technology; Lithography; MOSFET circuits; Oxidation; Random access memory; Stability; Thin film transistors;
Journal_Title :
Electron Devices, IEEE Transactions on
