Interface trap effect on gate induced drain leakage current in submicron N-MOSFET´s

Author

Wang, Tahui ; Huang, Chimoon ; Chang, T.E. ; Chou, J.W. ; Chang, C.Y.

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

41

Issue

12

fYear

1994

fDate

12/1/1994 12:00:00 AM

Firstpage

2475

Lastpage

2477

Abstract

An interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5/μm LATID N-MOSFET. In experiment, the interface traps were generated by hot carrier stress. The increased drain leakage current due to the band-trap-band tunneling can be adequately described by an analytical expression of ΔI_d=A exp(-B_u/F) with a value of B_u of 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling

Keywords

MOSFET; electron traps; hole traps; hot carriers; interface states; leakage currents; semiconductor device models; tunnelling; 0.5 micron; LATID N-MOSFET; band-trap-band tunneling; conduction band; electron tunneling; gate induced drain leakage current; hole tunneling; hot carrier stress; interface trap effect; model; submicron NMOSFET; tunneling mechanism; valence band; Charge carrier processes; Councils; Current measurement; Electron traps; Hot carriers; Interface states; Leakage current; MOSFET circuits; Occupational stress; Tunneling;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.337468

Filename

337468