• DocumentCode
    1208490
  • Title

    Power-conscious design of the Cell processor´s synergistic processor element

  • Author

    Takahashi, Osamu ; Cottier, Scott ; Dhong, Sang H. ; Flachs, Brian ; Silberman, Joel

  • Volume
    25
  • Issue
    5
  • fYear
    2005
  • Firstpage
    10
  • Lastpage
    18
  • Abstract
    The authors describe the low-power design of the synergistic processor element (SPE) of the cell processor developed by Sony, Toshiba and IBM. CMOS static gates implement most of the logic, and dynamic circuits are used in critical areas. Tight coupling of the instruction set architecture, microarchitecture, and physical implementation achieves a compact, power-efficient design.
  • Keywords
    CMOS logic circuits; instruction sets; logic design; logic gates; low-power electronics; microprocessor chips; CMOS static gates; Cell processor SPE; IBM; Sony; Toshiba; dynamic circuits; instruction set architecture; logic circuits; low-power design; microarchitecture; power-conscious design; synergistic processor element; CMOS logic circuits; Chip scale packaging; Data handling; HDTV; Image processing; Latches; Process design; Product development; Testing; Vehicles; CMOS; Cell Processor; SPE; Synergistic processor element; low power; power-conscious design;
  • fLanguage
    English
  • Journal_Title
    Micro, IEEE
  • Publisher
    ieee
  • ISSN
    0272-1732
  • Type

    jour

  • DOI
    10.1109/MM.2005.97
  • Filename
    1528451
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1208490