Title :
Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor
Author :
Asano, Toru ; Silberman, Joel ; Dhong, Sang H. ; Takahashi, Osamu ; White, Michael ; Cottier, Scott ; Nakazato, Takaaki ; Kawasumi, Atsushi ; Yoshihara, Hiroshi
Author_Institution :
IBM Eng. & Technol. Service, Japan
Abstract :
The synergistic processor element is a new architecture oriented for multimedia and streaming processing. In this architecture, the memory is not a cache but a private or scratch pad memory. Such a memory is simple and needs to be high-frequency and large space in low-power. This design uses an 11 fan-out of four (11FO4), six-cycle, fully pipelined, embedded 256-Kbyte SRAM for this purpose. The design´s memory is not one hard macro, but a group of custom macros physically distributed to optimize the pipeline.
Keywords :
SRAM chips; embedded systems; logic design; low-power electronics; microprocessor chips; 11FO4 256-Kbyte embedded SRAM; Cell processor; low-power design; macro; multimedia processing; scratch pad memory; streaming processing; synergistic processor element; Acceleration; Buffer storage; Decoding; Delay; Pipelines; Process design; Random access memory; Space technology; Streaming media; Testing; 11 fan-out of four; 11FO4; Cell processor; Synergistic Processor Element; multimedia processing; private memory; scratch pad memory; streaming processing;
Journal_Title :
Micro, IEEE
