DocumentCode
1208889
Title
Circuit layout and yield
Author
Kooperberg, Charles
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
Volume
23
Issue
4
fYear
1988
fDate
8/1/1988 12:00:00 AM
Firstpage
887
Lastpage
892
Abstract
The relation between circuit layout and yield is studied. A well-known yield formula is extended to a more general yield formula, in which not necessarily every defect is fatal. A defect sensitivity function is discussed. The function contains, in principle, all information about a chip layout necessary to calculate the yield. The relation between this sensitivity function and the yield formula is explained. If the defect size distribution is known the defect sensitivity function can be used to compute an optimal shrinking factor. An example, in which several defect size distributions are used, shows that these computations are highly sensitive for the form of the defect size distribution
Keywords
integrated circuit technology; optimisation; probability; circuit layout; defect sensitivity function; defect size distribution; optimal shrinking factor; yield formula; Circuit faults; Distributed computing; Integrated circuit modeling; Integrated circuit yield; Shape; Statistics;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.338
Filename
338
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