Voltage-Controlled Relaxation Oscillations in Phase-Change Memory Devices

Author

Ielmini, Daniele ; Mantegazza, Davide ; Lacaita, Andrea L.

Author_Institution

Dipt. di Elettron. e Inf., Politec. di Milano, Milan

Volume

29

Issue

6

fYear

2008

fDate

6/1/2008 12:00:00 AM

Firstpage

568

Lastpage

570

Abstract

A new oscillation behavior in a phase-change memory device is presented and analyzed. The device consists in a chalcogenide resistor with a parallel capacitance and no inductance. Biasing the device immediately after a proper trigger pulse leads to damped relaxation oscillations, which can be controlled in frequency by the bias voltage. The oscillation mechanism is explained by repetitive cycles of threshold switching and recovery of the high-resistance (off) state of the amorphous chalcogenide region in the device. Damping is explained by oscillation-induced phase change in the chalcogenide layer.

Keywords

memory architecture; oscillations; phase change materials; voltage control; bias voltage; chalcogenide layer; chalcogenide resistor; damped relaxation oscillations; oscillation behavior; oscillation-induced phase change; parallel capacitance; phase-change memory devices; threshold switching; trigger pulse; voltage-controlled relaxation oscillations; Amorphous semiconductors; chalcogenide; crystal growth; nonvolatile memories; phase-change memory (PCM); relaxation oscillator;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2008.921957

Filename

4510713