Title :
A novel trench capacitor enhancement approach by selective liquid-phase deposition
Author :
Lin, Shian-Jyh ; Lai, Chao-Sung ; Liao, Shian-Hau ; Chung-Yuan Lee ; Lee, Chung-Yuan ; Chiang, Shi-Ming ; Liang, Muh-Wang
Abstract :
For the first time, a novel and simple trench bottle integrated process is demonstrated on dynamic random access memory (DRAM) manufacturing by selective liquid phase deposition (S-LPD) oxide. After photoresist (PR) filled into a deep trench (DT) and was recess etched at around 1.3 μm depth, LPD oxide can be selected as a deposit onto the DT sidewall but not as a deposit on the PR surface. This S-LPD oxide is formed by using hexa-fluosilic acid (H2SiF6) and water without H3BO3. After the PR is removed, the LPD oxide becomes a protective layer on DT upper portion. Thus, the DT bottom area can be enlarged to form a trench bottle by NH4OH wet etching. Compared to conventional DT trench, 20% of capacitance was enhanced by this S-LPD process. This novel and low-cost method is for the first time demonstrated on 200-mm wafer 110-nm trench DRAM technology.
Keywords :
DRAM chips; etching; hydrogen compounds; liquid phase deposition; nanotechnology; nitrogen compounds; semiconductor process modelling; thin film capacitors; 110 nm; 200 mm; H2SiF6; NH4OH; S-LPD oxide; dynamic random access memory manufacturing; hexa-fluosilic acid; integrated circuit manufacture; nanotechnology; selective liquid phase deposition oxide; selective liquid-phase deposition; trench DRAM technology; trench bottle integrated process; trench capacitor enhancement approach; wet etching; Capacitance; Capacitors; Chaos; DRAM chips; Etching; Manufacturing; Oxidation; Random access memory; Resists; Silicon; Capacitance enhancement factor; selective liquid phase deposition (S-LPD); trench bottle;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
DOI :
10.1109/TSM.2005.858527
