DocumentCode :
1211220
Title :
VLSI test strategy planning techniques and tools
Author :
Baker, K. ; Croft, R.M.
Author_Institution :
GEC Research Limited, Hirst Research Centre, Wembley, UK
Volume :
4
Issue :
2
fYear :
1987
fDate :
4/1/1987 12:00:00 AM
Firstpage :
83
Lastpage :
88
Abstract :
The wide variety of current VLSI design styles means that different test methods and testability schemes are often required within a single design. This paper reviews new developments in digital system testability, especially that of test planning, in which a complex design is partitioned into a number of smaller blocks which can be tested individually.
Keywords :
VLSI; circuit analysis computing; integrated circuit testing; VLSI design styles; VLSI test strategy planning; circuit analysis computing; digital system testability;
fLanguage :
English
Journal_Title :
Computer-Aided Engineering Journal
Publisher :
iet
ISSN :
0263-9327
Type :
jour
DOI :
10.1049/cae:19870019
Filename :
4807056
Link To Document :
بازگشت