Electrical packaging requirements for low-voltage ICs-3.3 V high-performance CMOS devices as a case study

Motivated by reduced-power dissipation and increased demand for portable systems, supply voltage for ICs is scaled down from present 5 V. However, packaging these reduced supply voltage devices demands closer attention to electrical packaging requirements. This work focuses on high-performance CMOS device technology for 5 V and 3.3 V operations. Devices are housed in quad flat (QFP), ball grid array (BGA), and pin grid array (PGA) packages. Maintaining computational throughput (CTP) introduces comparable noise levels for 5 V and 3.3 V operations. This increases the probability of false switching in 3.3 V operation. Noise levels for lesser, comparable, and faster CTP 3.3 V packaged devices are given. False switching for 3.3 V operation is analyzed using receiver dynamic noise immunity. Packaged device performance and noise were measured to validate the modeling and simulation methodology, and general trends. “What if” study was performed to reduce simultaneous switching noise (SSN) using various techniques and their merits are explained