A CMOS GSM IF-sampling circuit with reduced in-channel aliasing

Author

Levantino, Salvatore ; Samori, Carlo ; Banu, Mihai ; Glas, Jack ; Boccuzzi, Vito

Author_Institution

Dipt. di Elettronica e Informazione, Politecnico di Milano, Italy

Volume

38

Issue

6

fYear

2003

fDate

6/1/2003 12:00:00 AM

Firstpage

895

Lastpage

904

Abstract

A complex intermediate frequency (IF) sampling technique with intrinsic rejection of even-order aliasing channels is demonstrated. The circuit subsamples in-phase and quadrature IF signals and uses a discrete-time analog delay and an adder to notch out the undesired aliasing frequencies. A chip designed in 0.25-μm CMOS technology demonstrates 27-dB antialiasing rejection for a 377-MHz IF GSM signal with 52-MHz sampling rate and 70-dB dynamic range.

Keywords

CMOS integrated circuits; cellular radio; mixed analogue-digital integrated circuits; radio receivers; sampled data circuits; signal sampling; switched capacitor networks; 0.25 micron; 377 MHz; 52 MHz; CMOS GSM IF-sampling circuit; CMOS technology; adder; complex intermediate frequency sampling technique; discrete-time analog delay; even-order aliasing channels; in-channel aliasing reduction; in-phase IF signals; quadrature IF signals; subsamples; Analog-digital conversion; Circuit testing; Filters; Frequency; GSM; Image sampling; Receivers; Sampling methods; Signal design; Signal to noise ratio;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.811871

Filename

1201991